Laser and plasma etch wafer dicing using water-soluble die attach film

ABSTRACT

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

BACKGROUND

1. Field

Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.

2. Description of Related Art

In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits known as dice.

Following the integrated circuit formation process, the wafer is “diced” to separate the individual die from one another for packaging or for use in an unpackaged form within larger circuits. The two main techniques that are used for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dice. These spaces are commonly referred to as “streets.” The diamond scribe forms shallow scratches in the wafer surface along the streets. Upon the application of pressure, such as with a roller, the wafer separates along the scribe lines. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about 10 mils (thousandths of an inch) or less in thickness. For thicker wafers, sawing is presently the preferred method for dicing.

With sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a supporting member such as an adhesive film stretched across a film frame and the saw is repeatedly applied to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dice. In addition, cracks can form and propagate from the edges of the dice into the substrate and render the integrated circuit inoperative. Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the <110> direction of the crystalline structure. Consequently, cleaving of the other side of the die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are maintained at a distance from the actual integrated circuits. As a result of the spacing requirements, not as many dice can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted. The use of a saw exacerbates the waste of real estate on a semiconductor wafer. The blade of the saw is approximate 15 microns thick. As such, to insure that cracking and other damage surrounding the cut made by the saw does not harm the integrated circuits, three to five hundred microns often must separate the circuitry of each of the dice. Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well. For example, one limitation hampering implementation of plasma dicing may be cost. A standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits.

SUMMARY

Embodiments of the present invention include methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.

In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

In another embodiment, a system for dicing a semiconductor wafer includes a factory interface. A laser scribe apparatus is coupled with the factory interface and includes a laser. A plasma etch chamber is also coupled with the factory interface. A wet/dry station is also coupled with the factory interface. The wet/dry station is configured to pattern a water-soluble die attach film.

In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits includes forming a mask above a silicon substrate. The silicon substrate is disposed on a water-soluble die attach film. The mask covers and protects integrated circuits disposed on the silicon substrate. The integrated circuits are composed of a layer of silicon dioxide disposed above a layer of low K material and a layer of copper. The mask, the layer of silicon dioxide, the layer of low K material, and the layer of copper are patterned with a laser scribing process to expose regions of the silicon substrate between the integrated circuits. The silicon substrate is then etched through the gaps to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a Flowchart representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention.

FIG. 2A illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operation 102 of the Flowchart of FIG. 1, in accordance with an embodiment of the present invention.

FIG. 2B illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operation 104 of the Flowchart of FIG. 1, in accordance with an embodiment of the present invention.

FIG. 2C illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations 106 and 108 of the Flowchart of FIG. 1, in accordance with an embodiment of the present invention.

FIG. 3 illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present invention.

FIGS. 4A-4F illustrate cross-sectional views of various operations in a method of dicing a semiconductor wafer, in accordance with an embodiment of the present invention.

FIG. 5 illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.

FIG. 6 illustrates a block diagram of an exemplary computer system, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as water-soluble die attach films for laser scribing and plasma etching singulation processes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

A hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch may be implemented for die singulation. The laser scribe process may be used to cleanly remove a mask, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. The plasma etch portion of the dicing process may then be employed to etch through the bulk of the wafer or substrate, such as through bulk single crystalline silicon, to yield die or chip singulation or dicing. A suitable die attach film for use with the laser scribe and plasma etch process may be a water-soluble die attach film which can be etched or partially dissolved with an aqueous solution.

As part of a singulation process, the to-be-diced device wafer may be mounted on a carrier tape or a carrier wafer. A die attach film (DAF) is typically applied between the carrier wafer (or tape) and the device wafer to hold the device wafer during dicing. After completion of the dicing process, the die attach film may also be singulated. Singulating the die attach film, while still attached to the device wafer, may be performed in order to enable removal of singulated dies for subsequent packaging and assembly processes. The singulation of the die attach film is typically performed via laser cutting in which the laser cuts are required to stop at the die attach film/carrier taper interface.

Throughput and dice contamination may be two issues with laser cutting a die attach film. For example, one possible disadvantage of using a laser to cut the die attach film is the low throughput. In a laser cutting die attach film process, debris from the die attach film may splash onto sidewall and top surface of dice. The die attach film may also carbonize. Subsequent cleaning processes may be needed to remove such contaminations in order to achieve desired yield. Much effort has been made to remove a cleaning step post die attach film laser cutting with little to no success. Furthermore, cleaning of the die attach film on the back side of each die can pose its own set of issues. For example, during laser cutting of a die attach film, the singulated dice are subjected to further exposure of laser radiation which potentially delivers thermal damage or debris to the dice. In accordance with an embodiment of the present invention, a water-soluble die attach film is used in a singulation process and is patterned with an aqueous solution, instead of with a laser.

FIG. 1 is a Flowchart 100 representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention. FIGS. 2A-2C illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations of Flowchart 100, in accordance with an embodiment of the present invention.

Referring to operation 102 of Flowchart 100, and corresponding FIG. 2A, a mask 202 is formed above a semiconductor wafer or substrate 204. The wafer or substrate 204 is disposed on a water-soluble die attach film 214. The mask 202 covers and protects integrated circuits 206 formed on the surface of semiconductor wafer 204. The mask 202 also covers intervening streets 207 formed between each of the integrated circuits 206.

In accordance with an embodiment of the present invention, forming the mask 202 includes forming a layer such as, but not limited to, a photo-resist layer or an I-line patterning layer. For example, a polymer layer such as a photo-resist layer may be composed of a material otherwise suitable for use in a lithographic process. In one embodiment, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a 248 nanometer (nm) resist, a 193 nm resist, a 157 nm resist, an extreme ultra-violet (EUV) resist, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, poly-cis-isoprene and poly-vinyl-cinnamate.

In an embodiment, semiconductor wafer or substrate 204 is composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably be disposed. For example, in one embodiment, semiconductor wafer or substrate 204 is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing semiconductor wafer 204 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, semiconductor wafer or substrate 204 is composed of a III-V material such as, e.g., a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

In an embodiment, semiconductor wafer or substrate 204 has disposed thereon or therein, as a portion of the integrated circuits 206, an array of semiconductor devices. Examples of such semiconductor devices include, but are not limited to, memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encased in a dielectric layer. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the integrated circuits 206. Conductive bumps and/or passivation layers may be formed above the interconnects layers. Materials making up the streets 207 may be similar to or the same as those materials used to form the integrated circuits 206. For example, streets 207 may be composed of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets 207 includes test devices similar to the actual devices of the integrated circuits 206.

Referring to operation 104 of Flowchart 100, and corresponding FIG. 2B, the mask 202 is patterned with a laser scribing process to provide a patterned mask 208 with gaps 210, exposing regions of the semiconductor wafer or substrate 204 between the integrated circuits 206. As such, the laser scribing process is used to remove the material of the streets 207 originally formed between the integrated circuits 206. In accordance with an embodiment of the present invention, patterning the mask 202 with the laser scribing process includes forming trenches 212 partially into the regions of the semiconductor wafer 204 between the integrated circuits 206, as depicted in FIG. 2B.

In an embodiment, patterning the mask 202 with the laser scribing process includes using a laser having a pulse width in the femtosecond range. Specifically, a laser with a wavelength in the visible spectrum or the ultra-violet (UV) or infra-red (IR) ranges (the three totaling a broadband optical spectrum) may be used to provide a femtosecond-based laser, i.e., a laser with a pulse width on the order of the femtosecond (10⁻¹⁵ seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask 202, the streets 207 and, possibly, a portion of the semiconductor wafer or substrate 204.

Laser parameters selection, such as pulse width, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. The cleaner the laser scribe cut, the smoother an etch process that may be performed for ultimate die singulation. In semiconductor device wafers, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

A street between individual integrated circuits disposed on a wafer or substrate may include the similar or same layers as the integrated circuits themselves. For example, FIG. 3 illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present invention.

Referring to FIG. 3, a street region 300 includes the top portion 302 of a silicon substrate, a first silicon dioxide layer 304, a first etch stop layer 306, a first low K dielectric layer 308 (e.g., having a dielectric constant of less than the dielectric constant of 4.0 for silicon dioxide), a second etch stop layer 310, a second low K dielectric layer 312, a third etch stop layer 314, an undoped silica glass (USG) layer 316, a second silicon dioxide layer 318, and a layer of photo-resist 320, with relative thicknesses depicted. Copper metallization 322 is disposed between the first and third etch stop layers 306 and 314 and through the second etch stop layer 310. In a specific embodiment, the first, second and third etch stop layers 306, 310 and 314 are composed of silicon nitride, while low K dielectric layers 308 and 312 are composed of a carbon-doped silicon oxide material.

Under conventional laser irradiation (such as nanosecond-based or picosecond-based laser irradiation), the materials of street 300 may behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based or picosecond-based laser irradiation. In an embodiment, however, a femtosecond-based laser process is used to pattern a layer of silicon dioxide, a layer of low K material, and a layer of copper by ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper. In a specific embodiment, pulses of approximately less than or equal to 400 femtoseconds are used in a femtosecond-based laser irradiation process to remove a mask, a street, and a portion of a silicon substrate.

In accordance with an embodiment of the present invention, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of 10 femtoseconds to 500 femtoseconds, although preferably in the range of 100 femtoseconds to 400 femtoseconds. In one embodiment, the femtosecond laser sources have a wavelength approximately in the range of 1570 nanometers to 200 nanometers, although preferably in the range of 540 nanometers to 250 nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot at the work surface approximately in the range of 3 microns to 15 microns, though preferably approximately in the range of 5 microns to 10 microns.

The spacial beam profile at the work surface may be a single mode (Gaussian) or have a shaped top-hat profile. In an embodiment, the laser source has a pulse repetition rate approximately in the range of 200 kHz to 10 MHz, although preferably approximately in the range of 500 kHz to 5 MHz. In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of 0.5 uJ to 100 uJ, although preferably approximately in the range of 1 uJ to 5 uJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of 500 mm/sec to 5 m/sec, although preferably approximately in the range of 600 mm/sec to 2 m/sec.

The scribing process may be run in single pass only, or in multiple passes, but, in an embodiment, preferably 1-2 passes. In one embodiment, the scribing depth in the work piece is approximately in the range of 5 microns to 50 microns deep, preferably approximately in the range of 10 microns to 20 microns deep. The laser may be applied either in a train of single pulses at a given pulse repetition rate or a train of pulse bursts. In an embodiment, the kerf width of the laser beam generated is approximately in the range of 2 microns to 15 microns, although in silicon wafer scribing/dicing preferably approximately in the range of 6 microns to 10 microns, measured at the device/silicon interface.

Laser parameters may be selected with benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of inorganic dielectrics (e.g., silicon dioxide) and to minimize delamination and chipping caused by underlayer damage prior to direct ablation of inorganic dielectrics. Also, parameters may be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth. As described above, a femtosecond-based laser is far more suitable to providing such advantages, as compared with picosecond-based and nanosecond-based laser ablation processes. However, even in the spectrum of femtosecond-based laser ablation, certain wavelengths may provide better performance than others. For example, in one embodiment, a femtosecond-based laser process having a wavelength closer to or in the UV range provides a cleaner ablation process than a femtosecond-based laser process having a wavelength closer to or in the IR range. In a specific such embodiment, a femtosecond-based laser process suitable for semiconductor wafer or substrate scribing is based on a laser having a wavelength of approximately less than or equal to 540 nanometers. In a particular such embodiment, pulses of approximately less than or equal to 400 femtoseconds of the laser having the wavelength of approximately less than or equal to 540 nanometers are used. However, in an alternative embodiment, dual laser wavelengths (e.g., a combination of an IR laser and a UV laser) are used.

Referring to operation 106 of Flowchart 100, and corresponding FIG. 2C, the semiconductor wafer 204 is etched through the gaps 210 in the patterned mask 208 to form singulated integrated circuits 206. In accordance with an embodiment of the present invention, etching the semiconductor wafer 204 includes etching the trenches 212 formed with the laser scribing process to ultimately etch entirely through semiconductor wafer 204, as depicted in FIG. 2C.

In an embodiment, etching the semiconductor wafer 204 includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer 204 is greater than 25 microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, Calif., USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling, which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer 204 at an etch rate greater than approximately 40% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally is a fluorine-based gas such as SF₆, C₄ F₈, CHF₃, XeF₂, or any other reactant gas capable of etching silicon at a relatively fast etch rate.

Referring to operation 108 of Flowchart 100, and again to corresponding FIG. 2C, the water-soluble die attach film 214 is patterned to provide die attach film portions 216 on each of the singulated integrated circuits 206. In one embodiment, water-soluble die attach film 214 is patterned by wet etching in an aqueous solution. In an embodiment, the water-soluble die attach film 214 is patterned in sequence following the laser scribe and plasma etch portions of the singulation process, as depicted in FIG. 2C. In an embodiment, the patterned mask 208 is removed after the laser scribe and plasma etch portions of the singulation process, as is also depicted in FIG. 2C. The patterned mask 208 may be removed prior to, during, or following patterning of the water-soluble die attach film 214, as described in more detail below in association with FIGS. 4A-4F.

Accordingly, referring again to Flowchart 100 and FIGS. 2A-2C, wafer dicing may be preformed by initial laser ablation through a mask, through wafer streets (including metallization), and partially into a silicon substrate. The laser pulse width may be selected in the femtosecond range. Die singulation may then be completed by subsequent through-silicon deep plasma etching. Furthermore, dissolution of exposed portions of the water-soluble die attach film is performed to provide singulated integrated circuits, each having a portion of a die attach film thereon. Furthermore, the mask layer may be removed during or following the above process. A specific example of a materials stack for dicing is described below in association with FIGS. 4A-4F, in accordance with an embodiment of the present invention.

Referring to FIG. 4A, a materials stack for hybrid laser ablation and plasma etch dicing includes a mask 402, a device layer 404, and a substrate 406. The mask 402, device layer 404, and substrate 406 are disposed above a water-soluble die attach film 408 which is affixed to a backing tape 410. In an embodiment, the mask 402 is a photo-resist layer such as the photo-resist layers described above in association with mask 202. The device layer 404 includes an inorganic dielectric layer (such as silicon dioxide) disposed above one or more metal layers (such as copper layers) and one or more low K dielectric layers (such as carbon-doped oxide layers). The device layer 404 may also include streets arranged between integrated circuits, the streets including the same or similar layers to the integrated circuits. In an embodiment, the substrate 406 is a bulk single-crystalline silicon substrate.

In an embodiment, the water-soluble die attach film 408 is a die attach film that is readily dissolvable in an aqueous media. For example, in one embodiment, the water-soluble die attach film 408 is composed of a material that is soluble in one or more of an alkaline solution, an acidic solution, or in deionized water. The water-soluble die attach film 408 may be suitable for bonding a thinned or thin wafer or substrate to the backing tape 410. In one embodiment, the water-soluble die attach film 408 has a thickness approximately in the range of 5-60 microns. In a specific embodiment, the water-soluble die attach film 408 has a thickness of approximately 20 microns.

In an embodiment, the water-soluble die attach film 408 maintains its water solubility upon a heating process, such as heating approximately in the range of 50-160 degrees Celsius. For example, in one embodiment, the water-soluble die attach film 408 is soluble in aqueous solutions following exposure to chamber conditions used in a laser and plasma etch singulation process. In one embodiment, the water-soluble die attach film 408 is composed of a material such as, but not limited to, polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethylene imine, or polyethylene oxide. In a specific embodiment, the water-soluble die attach film 408 has an etch rate in an aqueous solution approximately in the range of 1-15 microns per minute and, more particularly, approximately 1.3 microns per minute. In another specific embodiment, the water-soluble die attach film 408 is formed above the device layer 404 by a spin-on technique.

In an embodiment, the bulk single-crystalline silicon substrate 406 is thinned from the backside prior to being affixed to the water-soluble die attach film 408. In one such embodiment, the thinning is performed after forming or disposing the mask 402 above the device layer 404. However, in another such embodiment, the thinning is performed before forming or disposing the mask 402 above the device layer 404. The thinning may be performed by a backside grind process. In one embodiment, the bulk single-crystalline silicon substrate 406 is thinned to a thickness approximately in the range of 50-100 microns. It is important to note that, in an embodiment, the thinning is performed prior to a laser ablation and plasma etch dicing process. In an embodiment, the device layer 404 has a thickness approximately in the range of 2-3 microns.

Referring to FIG. 4B, the mask 402, the device layer 404 and a portion of the substrate 406 are patterned with a laser scribing process 412 to form trenches 414 in the substrate 406. In an embodiment, the laser scribing process 412 is a femtosecond-based laser scribing process 412. In an embodiment, the mask 402 is cut through by the laser scribing process 412 and functions to carry debris generated by the laser scribing process 412.

Referring to FIG. 4C, a through-silicon deep plasma etch process 416 is used to extend the trench 414 down to the die attach film 408, exposing the top portion of the water-soluble die attach film 408 and singulating the silicon substrate 406. The device layer 404 is protected by the mask 402 during the through-silicon deep plasma etch process 416.

Referring to FIG. 4D, the singulation process may further include patterning the water-soluble die attach film 408. In an embodiment, the water-soluble die attach film 408 is patterned by at least partial dissolution in an aqueous media. For example, in one embodiment, the water-soluble die attach film 408 is at least partially dissolved in a solution such as, but not limited to, an alkaline solution, an acidic solution, or deionized water. The patterning exposing the top portion of the backing tape 410 and singulates the water-soluble die attach film 408 to provide die attach film portions 418.

Thus, in accordance with an embodiment of the present invention, a water soluble die attach film is applied to a device wafer for singulation. The water soluble die attach film is applied onto the carrier taper or carrier wafer. After the laser scribing and subsequent silicon etch processes, the dies are singulated while portions of the die attach film along the wafer streets are exposed. The singulated device wafer is then, in one embodiment, dipped into or sprayed with a water-based solution to pattern the die attach film along the wafer streets.

The patterning of the water-soluble die attach film may include completely dissolving the exposed portions of the water-soluble die attach film through its entire thickness, while the majority of the die attach film underneath the singulated dice remains. In a specific embodiment, the open or exposed regions of the die attach film are approximately in the range of 10-60 microns wide and the die attach film is only approximately in the range of 5-50 microns thick. Meanwhile, the die size is approximately in the range of 7 millimeters×7 millimeters or larger. Thus, in an embodiment, a majority of the die attach film underneath each die is retained. For example, FIG. 4E illustrates an idealized result where the portions 418 of the water-soluble die attach film retained after patterning are flush with the edges of the individualized die 406. In another example, FIG. 4F illustrates a resultant aqueous solution patterning where the portions 418 of the water-soluble die attach film retained after patterning slightly undercut the edges of the individualized die 406.

Further embodiments may include subsequently removing the singulated portions of substrate 406 (e.g., as individual integrated circuits) from the backing tape 410. In one embodiment, the portions 418 singulated die attach film 408 are retained on the back sides of the singulated portions of substrate 406. In an embodiment, the singulated integrated circuits are removed from the backing tape 410 for packaging. In one such embodiment, the portions 418 of die attach film 408 are retained on the backside of each integrated circuit and included in the final packaging. However, in another embodiment, the portions 418 of die attach film 408 are removed during or subsequent to the singulation process, e.g., by extended aqueous solution treatment.

Further embodiments may include the removal of remaining portions of the mask 402. Mask 402 may be removed prior to, during, or subsequent to the patterning of water-soluble die attach film 408. In an embodiment, the mask 402 is also composed of a water-soluble material, and mask 402 is removed during the patterning of water-soluble die attach film 408.

Referring again to FIGS. 2A-2C, the plurality of integrated circuits 206 may be separated by streets 207 having a width of approximately 10 microns or smaller. The use of a femtosecond-based laser scribing approach, at least in part due to the tight profile control of the laser, may enable such compaction in a layout of integrated circuits. It is to be understood, however, that it may not always be desirable to reduce the street width to less than 10 microns even if otherwise enabled by a femtosecond-based laser scribing process. For example, some applications may require a street width of at least 40 microns in order to fabricate dummy or test devices in the streets separating the integrated circuits. In an embodiment, the plurality of integrated circuits 206 may be arranged on semiconductor wafer or substrate 204 in a non-restricted or freeform layout.

A single process tool may be configured to perform many or all of the operations in a hybrid laser ablation and plasma etch singulation process including the use of a water-soluble die attach film. For example, FIG. 5 illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.

Referring to FIG. 5, a process tool 500 includes a factory interface 502 (Fl) having a plurality of load locks 504 coupled therewith. A cluster tool 506 is coupled with the factory interface 502. The cluster tool 506 includes a plasma etch chamber 508. A laser scribe apparatus 510 is also coupled to the factory interface 502. The overall footprint of the process tool 500 may be, in one embodiment, approximately 3500 millimeters (3.5 meters) by approximately 3800 millimeters (3.8 meters), as depicted in FIG. 5.

In an embodiment, the laser scribe apparatus 510 houses a laser. In one such embodiment, the laser is a femtosecond-based laser. The laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process including the use of a mask, such as the laser abalation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus 500, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the laser. In a specific embodiment, the laser is also moveable. The overall footprint of the laser scribe apparatus 1210 may be, in one embodiment, approximately 2240 millimeters by approximately 1270 millimeters, as depicted in FIG. 5.

In an embodiment, the plasma etch chamber 508 is configured for etching a wafer or substrate through the gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the plasma etch chamber 508 is configured to perform a deep silicon etch process. In a specific embodiment, the plasma etch chamber 508 is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, Calif., USA. The plasma etch chamber 508 may be specifically designed for a deep silicon etch used to create singulate integrated circuits housed on or in single crystalline silicon substrates or wafers. In an embodiment, a high-density plasma source is included in the plasma etch chamber 508 to facilitate high silicon etch rates. In an embodiment, more than one plasma etch chamber is included in the cluster tool 506 portion of process tool 500 to enable high manufacturing throughput of the singulation or dicing process.

The factory interface 502 may be a suitable atmospheric port to interface between an outside manufacturing facility with laser scribe apparatus 510 and cluster tool 506. The factory interface 502 may include robots with arms or blades for transferring wafers (or carriers thereof) from storage units (such as front opening unified pods) into either cluster tool 506 or laser scribe apparatus 510, or both.

Cluster tool 506 may include other chambers suitable for performing functions in a method of singulation. For example, in one embodiment, in place of an additional etch chamber, a deposition chamber 512 is included. The deposition chamber 512 may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber 512 is suitable for depositing a photo-resist layer.

In an embodiment, a wet/dry station 514 is included for patterning or removing altogether a water-soluble die attach film. The wet/dry station may also be suitable for cleaning residues and fragments, or for removing a mask, subsequent to a laser scribe and plasma etch singulation process of a substrate or wafer. In an embodiment, a metrology station is also included as a component of process tool 500.

Embodiments of the present invention may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present invention. In one embodiment, the computer system is coupled with process tool 1200 described in association with FIG. 5. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

FIG. 6 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system 600 within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system 600 includes a processor 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 618 (e.g., a data storage device), which communicate with each other via a bus 630.

Processor 602 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 602 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 602 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor 602 is configured to execute the processing logic 626 for performing the operations described herein.

The computer system 600 may further include a network interface device 608. The computer system 600 also may include a video display unit 610 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse), and a signal generation device 616 (e.g., a speaker).

The secondary memory 618 may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) 631 on which is stored one or more sets of instructions (e.g., software 622) embodying any one or more of the methodologies or functions described herein. The software 622 may also reside, completely or at least partially, within the main memory 604 and/or within the processor 602 during execution thereof by the computer system 600, the main memory 604 and the processor 602 also constituting machine-readable storage media. The software 622 may further be transmitted or received over a network 620 via the network interface device 608.

While the machine-accessible storage medium 631 is shown in an exemplary embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

In accordance with an embodiment of the present invention, a machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps. Regions of the semiconductor wafer are exposed between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

Thus, methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, have been disclosed. In accordance with an embodiment of the present invention, a method includes dicing a semiconductor wafer having a plurality of integrated circuits includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a die attach film. The mask covers and protects the integrated circuits. The method also includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes etching the semiconductor wafer through the gaps in the patterned mask to form singulated integrated circuits. The method also includes patterning the water-soluble die attach film with an aqueous solution. In one embodiment, patterning the water-soluble die attach film with the aqueous solution includes singulating the water-soluble die attach film at an etch rate approximately in the range of 1-15 microns per minute. In one embodiment, forming the mask above the semiconductor wafer includes forming a water-soluble mask, and patterning the water-soluble die attach film with the aqueous solution further includes removing the water-soluble mask. 

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: forming a mask above the semiconductor wafer disposed on a water-soluble die attach film, the mask covering and protecting the integrated circuits; patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits; etching the semiconductor wafer through the gaps in the patterned mask to form singulated integrated circuits; and patterning the water-soluble die attach film with an aqueous solution.
 2. The method of claim 1, wherein patterning the water-soluble die attach film with the aqueous solution comprises singulating the water-soluble die attach film at an etch rate approximately in the range of 1-15 microns per minute.
 3. The method of claim 1, wherein forming the mask above the semiconductor wafer disposed on the water-soluble die attach film comprises forming the mask above the semiconductor wafer disposed on a film comprising a material selected from the group consisting of polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethylene imine, and polyethylene oxide.
 4. The method of claim 3, wherein the thickness of the film is approximately in the range of 5-60 microns.
 5. The method of claim 1, wherein patterning the water-soluble die attach film with the aqueous solution comprises using a solution selected from the group consisting of an alkaline solution, an acidic solution, and deionized water.
 6. The method of claim 1, wherein forming the mask above the semiconductor wafer comprises forming a water-soluble mask, and wherein patterning the water-soluble die attach film with the aqueous solution further comprises removing the water-soluble mask.
 7. The method of claim 1, wherein patterning the mask with the laser scribing process comprises patterning with a femtosecond-based laser scribing process, and wherein etching the semiconductor wafer through the gaps in the patterned mask comprises using a high density plasma etching process.
 8. A system for dicing a semiconductor wafer comprising a plurality of integrated circuits, the system comprising: a factory interface; a laser scribe apparatus coupled with the factory interface; a plasma etch chamber coupled with the factory interface; and a wet/dry station coupled with the factory interface, the wet/dry station configured to pattern a water-soluble die attach film.
 9. The system of claim 8, wherein the wet/dry station is configured to deliver an aqueous solution selected from the group consisting of an alkaline solution, an acidic solution, and deionized water.
 10. The system of claim 9, wherein the wet/dry station is configured to deliver the aqueous solution by filling a holding tank or by spraying.
 11. The system of claim 8, wherein the plasma etch chamber and the wet/dry station are housed on a cluster tool coupled with the factory interface, the cluster tool further comprising: a deposition chamber configured to form a water-soluble mask.
 12. The system of claim 11, wherein the wet/dry station is configured to remove the water-soluble mask during the patterning of the water-soluble die attach film.
 13. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: forming a mask above a silicon substrate disposed on a water-soluble die attach film, the mask covering and protecting integrated circuits disposed on the silicon substrate, the integrated circuits comprising a layer of silicon dioxide disposed above a layer of low K material and a layer of copper; patterning the mask, the layer of silicon dioxide, the layer of low K material, and the layer of copper with a laser scribing process to expose regions of the silicon substrate between the integrated circuits; etching the silicon substrate through the exposed regions form singulated integrated circuits; and patterning the water-soluble die attach film with an aqueous solution.
 14. The method of claim 13, wherein patterning the water-soluble die attach film with the aqueous solution comprises singulating the water-soluble die attach film at an etch rate approximately in the range of 1-15 microns per minute.
 15. The method of claim 13, wherein forming the mask above the silicon substrate disposed on the water-soluble die attach film comprises forming the mask above the silicon substrate disposed on a film comprising a material selected from the group consisting of polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethylene imine, and polyethylene oxide.
 16. The method of claim 15, wherein the thickness of the film is approximately in the range of 5-60 microns.
 17. The method of claim 13, wherein patterning the water-soluble die attach film with the aqueous solution comprises using a solution selected from the group consisting of an alkaline solution, an acidic solution, and deionized water.
 18. The method of claim 13, wherein forming the mask above the silicon substrate comprises forming a water-soluble mask, and wherein patterning the water-soluble die attach film with the aqueous solution further comprises removing the water-soluble mask.
 19. The method of claim 13, wherein patterning the mask, the layer of silicon dioxide, the layer of low K material, and the layer of copper with the laser scribing process comprises patterning with a femtosecond-based laser scribing process, and wherein etching the silicon substrate through the exposed regions comprises using a high density plasma etching process.
 20. The method of claim 13, wherein patterning the mask, the layer of silicon dioxide, the layer of low K material, and the layer of copper with the laser scribing process comprises ablating the mask prior to ablating the layer of silicon dioxide, and ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper. 